Design Spec/ RTL Coding
Preliminary Logic Synthesis
Functional & Timing Verification
Project Kickoff
Customer Site
Design & IP Qualification Check
Preliminary DFT Implementation
Functional Physical Design
Logic Re-Synthesis / Re-optimization
Functional & Timing Verification
Design & IP Qualification Check
DFT Implementation
DFT Result Checking
Physical Design Implementation
Design for Reliability
Design for Manufactury
STA
Post-layout Simulation
SI-based STA
ATPG/Function Simulation
Physical Verification
Tape-Out Process
Preliminary Design Handoff
Final Design Handoff
Pre-layout Sign-off
Post-layout Sign-off
Tape Out
uns, upad_assign, uck, usdifs
GUC9000, NC-Verilog
uns, uck, upad_assign, uptg.
Prime Time, GUC9000
uns, upad_assign,
Prime Time, NC-Verilog
uns, upad_assign, utpg,
Prime Time, NC-Verilog
Prime Time, NC-Verilog
uns, updc, usdfs,
Prime Time, NC-Verilog
umask_check
GUC Site