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- Code purification and coverage analysis
- PowerWise Advisor Platform for ultra low
power design
- Dynamic IR advisor
- DFT integration platform
- IP integration/GUC9000 IP quality checking
methodology
- Multi-level Hierarchical design and implementation
methodology
- DFM advisor - CAA/CMP/LPC Analysis and
Fixing
- High-speed interface simulation methodology
- One Pass Implementation platform
- Physical synthesis
. SI and timing aware implementation
. OCV ( On Chip Variation) analysis and prevention methodology
. Multiple RC analysis and prevention methodology
.Critical Area Analysis and Fixing
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 Sign-off
& Hand-off Tool |
Description |
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GUC9000 |
GUC
IP Model Checker |
|
uns |
Netlist
Quality Checker |
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upad_assign |
Pin
Sequence Checker |
| uck |
Clock Domain
Tracer |
| usdfs |
SDF
Checker |
| updc |
Multiple
Power Domain Checker |
| utpg |
Pattern
Translator |
| umask_check |
Mask Layer
and e-job Automatic Checker |
| NC-Verilog |
Simulation
Sign-off Tool |
| PrimeTime |
Static Timing
Analysis Sign-off Tool |
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