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| It is well known
that SiP technology can bring the following benefit to your
products: |
- Miniaturization : Lighter, Smaller, and
Thinner
- Better performance: Shorter trace distance
and reduction of Noise/Power Consumption/EMI
- Integration of heterogeneous and mixed
process technologies
- Lower total cost and better time-to-market
|
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| GUC has a deep
experience level in SiP service. As of Q109, we have shipped
15 million units to our customers. Nowadays, SiP services contribute
around 30% of our revenue. Following are some highlights of
SiP success stories: |
| |
| Application |
 KGD |
PKG |
Size (mmxmm) |
|
|
Network |
8x
RLDRAM, ~300 Passives |
FCBGA
|
55x72 |
|
Camcoder |
2
x MDDR
|
LFBGA
|
15X15 |
| Cellular
Phone |
PMIC,
SDRAM, Flash
|
PoP
|
12X12 |
| Security
Camera |
SDRAM
|
LFBGA |
12X12 |
| Multimedia |
SDRAM,
High speed PHY |
LFBGA |
14X14 |
| T-Con |
SDRAM |
LQFP
|
24X24 |
| Mobile-TV |
SDRAM
|
TFBGA |
12X12 |
| Car
Camera |
SDRAM,
Rx, Tx |
LFBGA |
14X14 |
| Mobile
TV |
RF,
~20 Passives
|
TFBGA |
12X12 |
| PC |
High speed PHY |
BGA |
23X23 |
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| GUC is certainly
your best choice for SiP service considering our proven track
record and for that we are at the most superior and effective
position in the total Integrated Circuit (IC) supply chain for
SiP design service that allows us in: |
- Known-Good-Die (KGD) identification,
sourcing and logistics.
- Optimization of SoC floor plan &
pad layout to match with KGD’s.
- Chip/Package/Board co-design to ensure
optimized package configuration, as well as performance
of electrical, thermal, mechanical and yield.
- Test flow and programming optimization for total test
solution of SoC & KGD.
|
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| Our time-tested
SiP design and production flow features full spectrum of services
that provide the optimal value to our customers: |
- A. Thorough Business Justification
- Feasibility study
- Trade-off analysis
- Cost assessment
- B. Complete Design Service
- From chip implementation to SiP package design
- From test development at chip and package levels to new
product introduction
- C. Total Engineering Solutions
- Design: Chip-package-board co-design to lower cost, risk
and optimize performance
- Electrical: Whole chip package modeling and timing analysis
- Thermal: 3D package modeling to obtain accurate junction
temperature
- Mechanical: CTE mismatch impact and stress analysis for
the entire package
- Design for Manufacturing (DFM): Whole chip routing Design
Rule Check (DRC) and layout optimization for assembly yield
improvement
- Design for Test (DFT): Embedded Built in Self Test (BIST)
circuit design and entire chip test solution
- Ecosystem: Easy access to engineering support from world
class PKG/Wafer foundries
- Total KGD solution
- D. Professional Manufacturing Service
- KGD logistics
- Production flow optimization and yield enhancement
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